A driver circuit is known that performs drive by changing over between a charging amplifier and a discharging amplifier for the full range drive on the high-potential side and the low-potential side. However, this type of driver circuit, if used in the driver circuit of a liquid crystal display device, would generate an output deviation in the output of each of the two amplifiers because of variations in the transistor characteristic. This increases the variation (termed as amplitude difference deviation) among outputs as to the voltage amplitude difference between the positive and negative polarities for the same grayscale level, sometimes resulting in degraded image quality. The amplitude difference deviation, one of performance characteristic of a multiple-output liquid crystal driver circuit, means a deviation in the outputs of the voltage amplitude difference in the positive polarity and the negative polarity at the same grayscale level. The smaller the amplitude difference deviation between the outputs is, the better the image quality is. The following describes a conventional driver circuit with the configuration in which drive is performed by changing over the two amplifiers, that is, a charging amplifier and a discharging amplifier.
FIG. 15 is a diagram showing an example of the circuit configuration of a conventional driver circuit with two amplifier circuits: a charging amplifier and a discharging amplifier. That is, FIG. 15 shows a driver circuit composed of a voltage follower circuit 910 and a voltage follower circuit 920.
The voltage follower circuit 910 comprises n-channel transistors 913 and 914 and p-channel transistors 911 and 912. The n-channel transistors 913 and 914, have their sources coupled together and connected to the low-potential power supply (ground potential) VSS via a constant-current source 915 and a switch 951, and have gates for differentially receiving the input terminal voltage Vin and output terminal voltage Vout respectively to compose a differential pair. The p-channel transistors 911 and 912 have their sources connected to the high-potential power supply VDD, have their gates connected each other, and have their drains connected respectively to the drains of the n-channel transistors 913 and 914. The drain and the gate of the p-channel transistor 912 are connected each other. The p-channel transistors 911 and 912 compose a current mirror circuit and function as the active load of the differential pair. The voltage follower circuit 910 further comprises a p-channel transistor 916. The gate of the p-channel transistor 916 is connected to the connection point (output end of differential pair) between the drain of the p-channel transistor 911 and the drain of the n-channel transistor 913, and the source is connected to the high-potential power supply VDD via a switch 952. A constant-current source 917 and a switch 953 are connected in series between the connection point, which are between the drain of the p-channel transistor 916 and the output terminal, and the low-potential power supply VSS.
The voltage follower circuit 920 comprises p-channel transistors 923 and 924 and n-channel transistors 921 and 922. The p-channel transistors 923 and 924, have their sources coupled together and connected to the high-potential power supply VDD via a constant-current source 925 and a switch 961, and have gates for differentially receiving the input terminal voltage Vin and output terminal voltage Vout respectively to compose differential pair. The n-channel transistors 921 and 922 have their sources connected to the low-potential power supply VSS, have their gates connected each other, and have their drains connected respectively to the drains of the p-channel transistors 923 and 924. The drain and the gate of the n-channel transistor 922 are connected each other. The n-channel transistors 921 and 922 compose a current mirror circuit and function as the active load of the differential pair. The voltage follower circuit 920 further comprises an n-channel transistor 926 which has a gate connected to a connection node at which the drain of the n-channel transistor 921 and the drain of the p-channel transistor 923 are connected, and a source connected to the low-potential power supply VSS via a switch 962. A constant-current source 927 and a switch 963 are connected in series between a connection node at which the drain of the n-channel transistor 926 and the output terminal are connected, and the high-potential power supply VDD.
Each of the circuits 910 and 920 composes a voltage follower circuit, wherein the input terminal voltage Vin is supplied to the non-inverting input terminal (gates of transistors 913 and 923) of the differential circuit and the output terminal voltage Vout is supplied to the inverting input terminal (gates of transistors 914 and 924) of the differential circuit.
The switches 951, 952, and 953 and the switches 961, 962, and 963 in the voltage follower circuits 910 and 920 are switches controlling the operation of the voltage follower circuits 910 and 920.
In the voltage follower circuit 910, although the output terminal Vout is discharged by the current source 917 at a constant discharging rate, the output terminal Vout may be charged speedily by the p-channel transistor 916.
On the other hand, in the voltage follower circuit 920, although the output terminal Vout is charged by the current source 927 at a constant discharging rate, the output terminal Vout may be discharged speedily by the n-channel transistor 926.
Therefore, to drive the load connected to the output terminal of the driver circuit to a high potential level with respect to the reference level, the switches 951, 952, and 953 are turned on to activate (operate) the voltage follower circuit 910. To drive the load to the low potential level with respect to the reference level, the switches 961, 962, and 963 are turned on to activate (operate) the voltage follower circuit 920 to perform high-speed drive.
In addition, because the voltage follower circuits 910 and 920 do not operate at the input voltage Vin that turns off the transistors 913 and 923, each of these circuits does not perform full-range drive (all region drive within power supply voltage range) by it self. Therefore, the two voltage follower circuits 910 and 920 are changed over for drive in order to perform full range drive.
However, the two voltage follower circuits 910 and 920 each have an output offset generated by variations in the device characteristic ascribable to fabrication process of the device.
A major cause of the output offset is generated in many cases by the variations in the characteristic of the paired transistors in the differential pair, or in the current mirror circuit included in the differential circuit which composes the voltage follower circuit.
Because variations in the transistor characteristic are generated arbitrarily, the output offsets of the two voltage follower circuits 910 and 920 are generated individually. Therefore, the problem is that, when the two-voltage follower circuits 910 and 920 are changed over to perform drive, the offset of the driver circuit in FIG. 15 varies greatly.
In particular, for a grayscale level voltage amplifier circuit in a liquid crystal device, it is important to keep constant the grayscale level voltage interval, determined according to the characteristic of liquid crystal, for performing a grayscale level display. It is therefore required for the amplifier circuit (driver circuit) that the output offset not be changed depending upon the grayscale level, that is, the deviation in the output offset among grayscale levels be sufficiently small.
However, when the driver circuit shown in FIG. 15 is used as the amplifier circuit for amplifying the grayscale level voltage of a liquid crystal display device, the problem is that, when the two voltage follower circuits 910 and 920 are changed over for drive, the output offset varies greatly with the result that the grayscale level voltage interval cannot be kept constant.
The problem described above is described more in detail with reference to FIG. 16. FIG. 16 is a diagram showing, with respect to the reference level, the expected values and the output values, including the offset, of a high level VL1 on a high-potential side and a low level VL2 on a low-potential side when they are driven by the driver circuit shown in FIG. 15. It is assumed that the high level VL1 is driven by the voltage follower circuit 910, and the low level VL2 by the voltage follower circuit 920, with the offsets being ±ΔVL1 and +ΔVL2, respectively. Whether or not the grayscale level voltage interval is kept constant is determined by whether or not the amplitude difference deviation in two grayscale levels is sufficiently small.
FIG. 16 shows that, for the amplitude difference deviation of two voltage levels VL1 and VL2, the maximum amplitude difference is{(VL1+ΔVL1)−(VL2−ΔVL2)}  (1)
and the minimum amplitude difference is{(VL1−ΔVL1)−(VL2+ΔVL2)}  (2).
Therefore, as the maximum value of the amplitude difference deviation which is given by the difference between the difference between expression (1) and expression (2), we have a following expression (3):{2×(ΔVL1+ΔVL2)}  (3)
That is, the amplitude difference deviation, which will be generated when the driver circuit in FIG. 15 is driven by changing over the two voltage follower circuits 910 and 920, may take a value that is twice the sum of the offset absolute values of the voltage follower circuits.
As mentioned in the above, the voltage follower circuits 910 and 920 shown in FIG. 15 do not operate at an input terminal voltage Vin that turns off the transistors 913 and 923 respectively. That is, the voltage-follower circuit 910 cannot drive a voltage in the vicinity of the low-potential power supply VSS, while the voltage follower circuit 920 cannot drive a voltage in the vicinity of the high-potential power supply VDD.
A full-range drive (the voltage is driven in all regions of power supply voltage range) is possible in the driver circuit in FIG. 15 by changing over between the voltage-follower circuits 910 and 920. However, a high-speed drive cannot be performed in the vicinity of the low-potential power supply VSS because the charge operation is performed by the current source 927, nor in the vicinity of the high-potential power supply VDD because the discharge operation is performed by the current source 917.
That is, the driver circuit shown in FIG. 15 cannot speedily drive a voltage within the power supply voltage range in an arbitrary order. In the configuration described above in which two conventional voltage follower circuits with different polarities are combined, a voltage in the vicinity of the power supply voltage (charge in the vicinity of VSS, discharge in the vicinity of VDD) cannot be driven speedily even if the two circuits are changed over for drive. Therefore, a voltage cannot be speedily driven in an arbitrary order.
FIG. 34 shows the configuration disclosed in Japanese Patent Publication Kokai JP-A-63-131707. This conventional circuit has the following configuration. In parallel to one transistor 1016 of paired transistors composing a differential pair used in the output stage of the amplifier, another MOS transistor 1034 is provided. A predetermined bias voltage BIAS2 is applied to the gate terminal of this MOS transistor 1034 to prevent the ionization of collision in the differential pair. The sources of the NMOS transistors 1014 and 1016, which form the differential pair, are coupled together and are connected to a current source 1020, the drain of the NMOS transistor 1014, which is one of transistors of the differential pair, is connected to the drain of a PMOS transistor 1010 in the output side of a current mirror circuit, and the drain of the NMOS transistor 1016 is connected to the drain of a PMOS transistor 1012 (the drain and the gate, which are connected, are connected to the gate of the PMOS transistor 1010) in the input side of the current mirror circuit. The drain of a transistor 1022, whose gate is connected to the connection point between the drain of the transistor 1010 and the drain of the transistor 1014, is connected to an output terminal, and the source of a transistor 1026, whose gate receives the output of an OP (Operational) amplifier 1040, is connected to the output terminal. The source of a transistor 1024, whose gate receives the output of the OP amplifier 1040, is connected to the gate of the transistor 1014. The transistors 1024 and 1026 form a source-follower. The input terminal voltage Vin is sent to a non-inverting input terminal (+) of the OP amplifier 1040, while the output terminal voltage Vout is sent to an inverting input terminal (−).
As the input terminal voltage Vin decreases, the output terminal voltage Vout also decreases. At this time, to prevent the ionization by collision from being caused by a high drain-gate voltage generated because the transistors 1014 and 1016 are turned off, the transistor 1034 is provided in parallel to the transistor 1016 whose gate is connected to the output terminal. This configuration allows the current to flow through the transistors 1012, 1034, 1020, and 1018 even if the transistors 1014 and 1016 are off to keep the drain-source voltage of the transistors 1014 and 1016 within a predetermined range.
The circuit shown in FIG. 34, which is configured by adding a transistor to the inverting input terminal side where the output voltage of the differential pair is received, is completely different from the circuit according to the present invention in the configuration and effect as will be described later. For example, the additional transistor 1034, if provided in the input side in the circuit shown in FIG. 34, would affect the operation of the amplifier. This requires the additional transistor 1034 to be provided in the inverting input terminal side (side connected to the output terminal voltage).